Invention Grant
- Patent Title: Method for forming inlaid interconnect
-
Application No.: US12247507Application Date: 2008-10-08
-
Publication No.: US07648908B2Publication Date: 2010-01-19
- Inventor: Nobuo Aoi
- Applicant: Nobuo Aoi
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2007-266681 20071012
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
After a groove is formed in an insulating layer formed on a semiconductor substrate, a barrier metal layer is formed on the insulating layer by an ALD process so as to cover the side walls and bottom of the groove, and an impurity layer is formed in or on the surface of the barrier metal layer by an ion implantation process or by an ALD process. Thereafter, the barrier metal layer and the impurity layer are alloyed, and then an inlaid interconnect layer, which is composed of a Cu seed layer and a Cu plating layer, is formed in the groove. Then, an impurity element in the alloyed barrier metal layer is thermally diffused into the inlaid interconnect layer.
Public/Granted literature
- US20090098726A1 METHOD FOR FORMING INLAID INTERCONNECT Public/Granted day:2009-04-16
Information query
IPC分类: