Invention Grant
US07649265B2 Micro-via structure design for high performance integrated circuits
有权
微通道结构设计用于高性能集成电路
- Patent Title: Micro-via structure design for high performance integrated circuits
- Patent Title (中): 微通道结构设计用于高性能集成电路
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Application No.: US11541124Application Date: 2006-09-29
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Publication No.: US07649265B2Publication Date: 2010-01-19
- Inventor: Chunfei Ye , Boping Wu
- Applicant: Chunfei Ye , Boping Wu
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent David L. Guglielmi
- Main IPC: H01L23/498
- IPC: H01L23/498
Abstract:
In some embodiments, a micro-via structure design for high performance integrated circuits is presented. In this regard, an integrated circuit chip package is introduced having a dielectric layer, a plated throughhole in the dielectric layer, and a micro-via coupled with the plated throughhole, wherein the micro-via forms a path around an axis. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US20080079139A1 Micro-via structure design for high performance integrated circuits Public/Granted day:2008-04-03
Information query
IPC分类:
