Invention Grant
US07649361B2 Methods for forming process test capacitors for testing embedded passives during embedment into a printed wiring board
失效
在嵌入印刷电路板期间形成用于测试嵌入式无源器件的工艺测试电容器的方法
- Patent Title: Methods for forming process test capacitors for testing embedded passives during embedment into a printed wiring board
- Patent Title (中): 在嵌入印刷电路板期间形成用于测试嵌入式无源器件的工艺测试电容器的方法
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Application No.: US11612089Application Date: 2006-12-18
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Publication No.: US07649361B2Publication Date: 2010-01-19
- Inventor: William Borland , Saul Ferguson , Diptarka Majumdar , Daniel I. Amey
- Applicant: William Borland , Saul Ferguson , Diptarka Majumdar , Daniel I. Amey
- Applicant Address: US DE Wilmington
- Assignee: E.I. du Pont de Nemours and Company
- Current Assignee: E.I. du Pont de Nemours and Company
- Current Assignee Address: US DE Wilmington
- Main IPC: G01R31/18
- IPC: G01R31/18
Abstract:
Making process test capacitors simultaneously with circuit capacitors that are to be embedded into a printed wiring board and firing the test capacitors to result in fired-on-foil test capacitors for the purpose of using the test capacitors as test substitutes for the embedded circuit capacitors to predict whether capacitance, dissipation factor or insulation resistance of the circuit capacitors will fall within acceptable specified ranges prior to and after embedment.
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