Invention Grant
US07649379B2 Reducing mission signal output delay in IC having mission and test modes
有权
降低使命和测试模式的IC任务信号输出延迟
- Patent Title: Reducing mission signal output delay in IC having mission and test modes
- Patent Title (中): 降低使命和测试模式的IC任务信号输出延迟
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Application No.: US11964323Application Date: 2007-12-26
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Publication No.: US07649379B2Publication Date: 2010-01-19
- Inventor: John Joseph Seibold
- Applicant: John Joseph Seibold
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Dawn V. Stephens; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03K19/00
- IPC: H03K19/00
Abstract:
An integrated circuit apparatus includes a switching circuit that provides respective signal paths to permit a mission signal, a test signal, and a boundary scan test signal to share an output terminal. The signal path associated with the mission signal imposes a smaller switching delay than do the signal paths associated with the test and boundary scan test signals.
Public/Granted literature
- US20090171611A1 Reducing Mission Signal Output Delay in IC Having Mission and Test Modes Public/Granted day:2009-07-02
Information query
