A multi-stage non-overlapping clock signal generator as described herein is suitable for use with a pipelined analog-to-digital converter architecture. The clock signal generator generally includes a back end clock generator, a second stage clock generator, and a first stage clock generator coupled in series. The clock signal generator may also include any number of intermediate stage clock generators coupled in series between the back end clock generator and the second stage clock generator. Example implementations of the various clock generator stages are also described herein.