An integrated circuit device is described. The circuit device may include a group of signal nodes, including a first signal node and a second signal node, a transmitter coupled to the group of signal nodes, and a first clock circuit coupled to the transmitter. The transmitter may transmit a first signal on the first signal node and a second signal on the second signal node. The first signal and the second signal may correspond to a first sequence of data bits during a sequence of bit times. The first clock circuit may control a transmit time of at least one of the first signal and the second signal. The first clock circuit may include a first phase adjustment element that provides compensation for a first timing offset between the first signal and the second signal. The first timing offset may be less than a bit time in the sequence of bit times.