A method and apparatus for conveying test stimulus data from an ATE system to an integrated circuit (IC) via a plesiochronous interconnect. The IC includes a core logic unit and a first receiver coupled to the core logic unit by a first data path. The first receiver includes an input having an interconnect coupled thereto. In a normal mode of operation, the first receiver is configured to receive data transmitted plesiochronously over the interconnect and to convey the data, via the first data path, to the core logic unit. The integrated circuit also includes a second data path coupled between the core logic unit and the interconnect. In a test mode, the core logic unit is configured to receive test stimulus data conveyed synchronously over the second data path, wherein the test stimulus data is received by the IC from the ATE via the interconnect.