Invention Grant
- Patent Title: Digital design component with scan clock generation
- Patent Title (中): 具有扫描时钟产生的数字设计组件
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Application No.: US11174193Application Date: 2005-07-01
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Publication No.: US07650549B2Publication Date: 2010-01-19
- Inventor: Charles M. Branch , Steven C. Bartling , Marc Edward Royer , Cory Dean Stewart
- Applicant: Charles M. Branch , Steven C. Bartling , Marc Edward Royer , Cory Dean Stewart
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent John J. Patti; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/40

Abstract:
A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of delay buffers in the scan mode data paths. Resulting application circuits have reduced circuit area, power consumption and noise generation. A clock generator for scan mode clocking is provided to obtain the separate, non-overlapping scan mode clocks. Scan mode clocks may be generated with a toggle flip flop, a pulse generator or a clock gating circuit.
Public/Granted literature
- US20070022339A1 Digital design component with scan clock generation Public/Granted day:2007-01-25
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