Invention Grant
- Patent Title: Method for modeling and verifying timing exceptions
- Patent Title (中): 用于建模和验证时序异常的方法
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Application No.: US11749090Application Date: 2007-05-15
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Publication No.: US07650581B2Publication Date: 2010-01-19
- Inventor: Solaiman Rahim , Mayank Jain
- Applicant: Solaiman Rahim , Mayank Jain
- Applicant Address: US CA San Jose
- Assignee: Atrenta, Inc.
- Current Assignee: Atrenta, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Sughrue Mion, PLLC
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method and system for timing exception verification in integrated circuit (IC) designs included verification of functional false paths as well as multi-cycle paths (MCPs). A false path or a MCP is modeled to a satisfiability formula and the formula is validated using a Boolean satisfiability solver. Time required for timing exception verification can be significantly reduced.
Public/Granted literature
- US20080288904A1 METHOD FOR MODELING AND VERIFYING TIMING EXCEPTIONS Public/Granted day:2008-11-20
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