Invention Grant
- Patent Title: Circuit analysis device allowing more accurate analysis of signal propagation delay in circuit representation of a highly abstract level
- Patent Title (中): 电路分析装置可以更准确地分析高抽象电平的电路表示中的信号传播延迟
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Application No.: US11753467Application Date: 2007-05-24
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Publication No.: US07650582B2Publication Date: 2010-01-19
- Inventor: Katsuharu Suzuki
- Applicant: Katsuharu Suzuki
- Applicant Address: JP
- Assignee: NEC Corporation
- Current Assignee: NEC Corporation
- Current Assignee Address: JP
- Agency: Hayes Soloway P.C.
- Priority: JP2006-148154 20060529
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
The present invention provides a circuit analysis device including: storage unit having stored therein: connection information about multiple components; delay information including information about the delay time of a discrete component and a chain delay time which is a delay time in the case in which a chain delay effect is generated by a connection with another component about each kind of the multiple components; and chain effect propagating component information including information about kinds of chain effect propagating components which are components for transmitting the chain delay effect, and data processing unit for: referring to the information stored in the storage unit; performing a total delay time calculation process of sequentially adding the delay times of the components along a signal path in the circuit; and if the chain effect propagating component is halfway through the signal path in the total delay time calculation process, examining a connection relation between components that precede and follow the chain effect propagating component and determining a delay time of the component that follows the chain effect propagating component that corresponds to the connection relations.
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