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US07651941B2 Method of manufacturing a semiconductor device that includes forming a via hole through a reaction layer formed between a conductive barrier and a wiring 失效
一种制造半导体器件的方法，包括通过形成在导电屏障和布线之间的反应层形成通孔

  • Patent Title: Method of manufacturing a semiconductor device that includes forming a via hole through a reaction layer formed between a conductive barrier and a wiring
  • Patent Title (中): 一种制造半导体器件的方法，包括通过形成在导电屏障和布线之间的反应层形成通孔
  • Application No.: US11892925
    Application Date: 2007-08-28
  • Publication No.: US07651941B2
    Publication Date: 2010-01-26
  • Inventor: Takashi Ishigami
  • Applicant: Takashi Ishigami
  • Applicant Address: JP Kawasaki, Kanagawa
  • Assignee: NEC Electronics Corporation
  • Current Assignee: NEC Electronics Corporation
  • Current Assignee Address: JP Kawasaki, Kanagawa
  • Agency: McGinn IP Law Group, PLLC
  • Priority: JP2006-233819 20060830
  • Main IPC: H01L21/4763
  • IPC: H01L21/4763
Method of manufacturing a semiconductor device that includes forming a via hole through a reaction layer formed between a conductive barrier and a wiring
Abstract:
Provided are: a method of manufacturing semiconductor device which has multilayer interconnection in a damascene structure and a conductive barrier film such as CoWP film, and which has more excellent electric characteristics than a conventional one. To this end, when a via hole reaching a lower wiring is formed, a reaction layer formed between a conductive barrier film and the lower wiring and remaining on the surface of the lower wiring is removed. Thus, at an interface where a lower surface of the via and the lower wiring are joined, the reaction layer, formed between the conductive barrier film and the lower wiring, does not exist, so that the via resistance can be sufficiently reduced.
Abstract(Chinese):

提供：一种制造在镶嵌结构中具有多层互连并且具有诸如CoWP膜的导电阻挡膜的半导体器件的方法，并且具有比常规的更优异的电特性。 为此，当形成到达下布线的通孔时，除去形成在导电阻挡膜和下布线之间并保留在下布线表面上的反应层。 因此，在通孔的下表面和下布线接合的界面处，形成在导电阻挡膜和下布线之间的反应层不存在，从而可以充分降低通孔电阻。

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IPC分类:
H 电学
H01 基本电气元件
H01L 半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00 专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02 .半导体器件或其部件的制造或处理
H01L21/04 ..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34 ...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/46 ....用H01L21/36至H01L21/428各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/44）
H01L21/461 .....改变半导体材料的表面物理特性或形状的，例如腐蚀、抛光、切割
H01L21/4763 ......非绝缘层的沉积，例如绝缘层上的导电层、电阻层；这些层的后处理（电极的制造入H01L21/28）
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