Invention Grant
US07652307B2 Semiconductor device with two overlapping diffusion layers held at floating voltage for improving withstand voltage
有权
具有两个重叠扩散层的半导体器件保持在浮动电压以提高耐受电压
- Patent Title: Semiconductor device with two overlapping diffusion layers held at floating voltage for improving withstand voltage
- Patent Title (中): 具有两个重叠扩散层的半导体器件保持在浮动电压以提高耐受电压
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Application No.: US11516733Application Date: 2006-09-07
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Publication No.: US07652307B2Publication Date: 2010-01-26
- Inventor: Shuichi Kikuchi , Kiyofumi Nakaya , Shigeaki Okawa
- Applicant: Shuichi Kikuchi , Kiyofumi Nakaya , Shigeaki Okawa
- Applicant Address: JP Osaka
- Assignee: Sanyo Electric Co., Ltd.
- Current Assignee: Sanyo Electric Co., Ltd.
- Current Assignee Address: JP Osaka
- Agency: Morrison & Foerster LLP
- Priority: JP2005-263468 20050912
- Main IPC: H01L29/00
- IPC: H01L29/00

Abstract:
In a semiconductor device of the present invention, a MOS transistor is disposed in an elliptical shape. Linear regions in the elliptical shape are respectively used as the active regions, and round regions in the elliptical shape is used respectively as the inactive regions. In each of the inactive regions, a P type diffusion layer is formed to coincide with a round shape. Another P type diffusion layer is formed in a part of one of the inactive regions. These P type diffusion layers are formed as floating diffusion layers, are capacitively coupled to a metal layer on an insulating layer, and assume a state where predetermined potentials are respectively applied thereto. This structure makes it possible to maintain current performance of the active regions, while improving the withstand voltage characteristics in the inactive regions.
Public/Granted literature
- US20070057321A1 Semiconductor device Public/Granted day:2007-03-15
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