Invention Grant
- Patent Title: Semiconductor memory device including a stacked gate having a charge storage layer and a control gate, and method of manufacturing the same
- Patent Title (中): 包括具有电荷存储层和控制栅极的堆叠栅极的半导体存储器件及其制造方法
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Application No.: US11940838Application Date: 2007-11-15
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Publication No.: US07652319B2Publication Date: 2010-01-26
- Inventor: Daisuke Tsurumi , Mitsuhiro Noguchi , Haruhiko Koyama
- Applicant: Daisuke Tsurumi , Mitsuhiro Noguchi , Haruhiko Koyama
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2006-311789 20061117
- Main IPC: H01L29/94
- IPC: H01L29/94
Abstract:
A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.
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