Invention Grant
- Patent Title: Solid-state imaging device and method for manufacturing same
- Patent Title (中): 固态成像装置及其制造方法
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Application No.: US10963849Application Date: 2004-10-13
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Publication No.: US07652343B2Publication Date: 2010-01-26
- Inventor: Keiji Mabuchi
- Applicant: Keiji Mabuchi
- Applicant Address: JP Tokyo
- Assignee: Sony Corporation
- Current Assignee: Sony Corporation
- Current Assignee Address: JP Tokyo
- Agency: Rockey, Depke & Lyons, LLC
- Agent Robert J. Depke
- Priority: JPP2001-281295 20010917
- Main IPC: H01L31/058
- IPC: H01L31/058

Abstract:
The reduction in size, noise and voltage is realized in a MOS solid-state imaging device. A gate electrode in a pixel part is formed in a two-level structure. An amplifier gate of an amplifier transistor is formed in the first level while a select gate of a select transistor is formed in the second level. The both are structurally partly overlapped. With the first-level amplifier gate as self-alignment, ions are implanted for a select gate in the second level. Although the gate electrode if formed in one level as in the conventional requires a space of nearly a design rule between the amplifier gate and the select gate, the structure of the invention can eliminate such a dead space. Meanwhile, because the diffusion layer does not exist between the amplifier gate and the select gate, the diffusion layer is eliminated of sheet resistance and voltage drop. Also, the resistance and voltage decrease, resulting from the LDD region of a transistor gate end, are eliminated in one end of the amplifier gate and in one end of the select gate.
Public/Granted literature
- US20050062068A1 Solid-state imaging device and method for manufacturing same Public/Granted day:2005-03-24
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