Invention Grant
- Patent Title: Substrate and process for semiconductor flip chip package
- Patent Title (中): 半导体倒装芯片封装的衬底和工艺
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Application No.: US11496111Application Date: 2006-07-31
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Publication No.: US07652374B2Publication Date: 2010-01-26
- Inventor: Chi Wah Kok , Yee Ching Tam
- Applicant: Chi Wah Kok , Yee Ching Tam
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A semiconductor package structure for flip chip package includes at least a patterned circuit layer and an insulating layer alternately stacking up each other. The patterned layer includes a plurality of bump pads, and the insulating layer includes a plurality of etching holes. The etching holes and the bump pads are aligned, such that the bump pads are exposed through the etching holes. A plurality of bumps is disposed on the active surface of the chip, which can be obtained by stud bumping. The etching holes are filled with solder paste, and the bumps of the chips penetrate into the solder filled etching holes. Vibration obtained by mechanical equipment, or ultrasonic equipment can be applied to assist the alignment of the bumps to the corresponding bump pads. A reflow process is applied to collapse the solder paste that fills the etching holes to form electrical connection between the bumps and bump pads.
Public/Granted literature
- US20080023829A1 Substrate and process for semiconductor flip chip package Public/Granted day:2008-01-31
Information query
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