Invention Grant
US07652903B2 Hit ahead hierarchical scalable priority encoding logic and circuits
失效
提前分级可扩展优先级编码逻辑和电路
- Patent Title: Hit ahead hierarchical scalable priority encoding logic and circuits
- Patent Title (中): 提前分级可扩展优先级编码逻辑和电路
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Application No.: US11073116Application Date: 2005-03-04
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Publication No.: US07652903B2Publication Date: 2010-01-26
- Inventor: Xiaohua Huang
- Applicant: Xiaohua Huang
- Applicant Address: US CA San Jose
- Assignee: Xiaohua Huang
- Current Assignee: Xiaohua Huang
- Current Assignee Address: US CA San Jose
- Main IPC: G11C15/00
- IPC: G11C15/00

Abstract:
In this invention a hit ahead multi-level hierarchical scalable priority encoding logic and circuits are disclosed. The advantage of hierarchical priority encoding is to improve the speed and simplify the circuit implementation and make circuit design flexible and scalable. To reduce the time of waiting for previous level priority encoding result, hit signal is generated first in each level to participate next level priority encoding, and it is called Hit Ahead Priority Encoding (HAPE) encoding. The hierarchical priority encoding can be applied to the scalable architecture among the different sub-blocks and can also be applied with in one sub-block. The priority encoding and hit are processed completely parallel without correlation, and the priority encoding, hit generation, address encoding and MUX selection of the address to next level all share same structure of circuits.
Public/Granted literature
- US20050198431A1 Priority encoding logic and circuits Public/Granted day:2005-09-08
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