A semiconductor memory device includes a pulse signal generator configured to combine a plurality of external command signals to generate a normal register control signal and an extended register control signal in response to a clock signal; a reset signal generator configured to receive operating information of a delay locked loop (DLL) circuit from an outside to generate a reset signal for a reset operation of the DLL circuit in response to the normal register control signal or the extended register control signal; and the DLL circuit configured to perform a reset operation in response to the reset signal.