Invention Grant
US07653072B2 Overcoming access latency inefficiency in memories for packet switched networks
失效
克服分组交换网络存储器中的访问延迟低效率
- Patent Title: Overcoming access latency inefficiency in memories for packet switched networks
- Patent Title (中): 克服分组交换网络存储器中的访问延迟低效率
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Application No.: US10494848Application Date: 2002-11-13
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Publication No.: US07653072B2Publication Date: 2010-01-26
- Inventor: Koen Deforche , Geert Verbruggen , Luc De Coster
- Applicant: Koen Deforche , Geert Verbruggen , Luc De Coster
- Applicant Address: US CT Shelton
- Assignee: Transwitch Corporation
- Current Assignee: Transwitch Corporation
- Current Assignee Address: US CT Shelton
- Agency: Gordon & Jacobson, PC
- International Application: PCT/US02/36278 WO 20021113
- International Announcement: WO03/043272 WO 20030522
- Main IPC: H04L12/28
- IPC: H04L12/28 ; G06F13/00 ; G11C8/00
Abstract:
A method buffering packets in a packet switching network (FIG. 5) includes receiving a packet from the network; splitting the packet into a plurality of PDUs; stripping at least some of the PDUs over a plurality of memory banks; (18) retrieving the PDUs from the memory banks: and at least temporarily storing the retrieved PDUs in the sequence they are to be transmitted. An apparatus for implementing the method is also disclosed.
Public/Granted literature
- US20050025140A1 Overcoming access latency inefficiency in memories for packet switched networks Public/Granted day:2005-02-03
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