Invention Grant
- Patent Title: Method and mechanism for modeling interconnect structures for integrated circuits
- Patent Title (中): 集成电路互连结构建模方法及机制
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Application No.: US11404636Application Date: 2006-04-13
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Publication No.: US07653519B1Publication Date: 2010-01-26
- Inventor: David Overhauser
- Applicant: David Overhauser
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Disclosed are methods, systems, and structures for implementing interconnect modeling by using a test structure which include a variation of physical wire structures between local interconnects and distant interconnects. According to one approach, the impact of variations of the physical properties for neighborhood wires are considered for the electrical modeling of interconnects. This variation between the local and distant wire characteristics allows more accurate and robust interconnect modeling to be created.
Public/Granted literature
- US2095417A Farm implement hitch Public/Granted day:1937-10-12
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