Invention Grant
US07653763B2 Subsystem boot and peripheral data transfer architecture for a subsystem of a system-on- chip
有权
子系统引导和外设数据传输架构，用于系统级芯片的子系统
- Patent Title: Subsystem boot and peripheral data transfer architecture for a subsystem of a system-on- chip
- Patent Title (中): 子系统引导和外设数据传输架构，用于系统级芯片的子系统
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Application No.: US10469529Application Date: 2002-02-28
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Publication No.: US07653763B2Publication Date: 2010-01-26
- Inventor: Mileend Gadkari , Harsimran S. Grewal , George Apostol, Jr.
- Applicant: Mileend Gadkari , Harsimran S. Grewal , George Apostol, Jr.
- Applicant Address: US CA Mountain View
- Assignee: Cavium Networks, Inc.
- Current Assignee: Cavium Networks, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Hamilton, Brook, Smith & Reynolds, P.C.
- International Application: PCT/US02/06331 WO 20020228
- International Announcement: WO02/069157 WO 20020906
- Main IPC: G06F13/28
- IPC: G06F13/28 ; G06F15/177
Abstract:
A subsystem (200) is provided at least Direct Memory Access (DMA) device (220) utilized to provide instructions to facilitate the operation of a subsystem processor (210). In one embodiment, a system level processor (102) initiates the provision of instructions for a subsystem (210). The DMA device may be additionally or alternatively utilized to provide data transfer capabilities to a plurality of data channels in a subsystem (200). The DMA device processes channels in a time limited manner to ensure that data is processed in a manner appropriate for time critical data.
Public/Granted literature
- US20040186930A1 Subsystem boot and peripheral data transfer architecture for a subsystem of a system-on- chip Public/Granted day:2004-09-23
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