Invention Grant
- Patent Title: Delay fault detection using latch with error sampling
- Patent Title (中): 使用具有错误采样的锁存器延迟故障检测
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Application No.: US11758124Application Date: 2007-06-05
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Publication No.: US07653850B2Publication Date: 2010-01-26
- Inventor: James W. Tschanz , Keith A. Bowman , Nam Sung Kim , Chris Wilkerson , Shih-Lien L. Lu , Tanay Karnik
- Applicant: James W. Tschanz , Keith A. Bowman , Nam Sung Kim , Chris Wilkerson , Shih-Lien L. Lu , Tanay Karnik
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Buckley, Maschoff & Talwalkar LLC
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G06K5/04
Abstract:
Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value.
Public/Granted literature
- US20080307277A1 DELAY FAULT DETECTION USING LATCH WITH ERROR SAMPLING Public/Granted day:2008-12-11
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