Invention Grant
US07653889B2 Method and apparatus for repeat execution of delay analysis in circuit design
失效
在电路设计中重复执行延迟分析的方法和装置
- Patent Title: Method and apparatus for repeat execution of delay analysis in circuit design
- Patent Title (中): 在电路设计中重复执行延迟分析的方法和装置
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Application No.: US11524342Application Date: 2006-09-20
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Publication No.: US07653889B2Publication Date: 2010-01-26
- Inventor: Izumi Nitta , Toshiyuki Shibuya , Katsumi Homma , Hidetoshi Matsuoka
- Applicant: Izumi Nitta , Toshiyuki Shibuya , Katsumi Homma , Hidetoshi Matsuoka
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Fujitsu Patent Center
- Priority: JP2006-081707 20060323
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/45

Abstract:
An apparatus includes: a detecting unit that detects a target path from among a plurality of paths in a target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the target path; an extracting unit that extracts delay data of a second circuit component having an identical type to that of the first circuit component; and a generating unit that generates a directive for replacing the first circuit component with the second circuit component.
Public/Granted literature
- US20070226669A1 Method and apparatus for repeat execution of delay analysis in circuit design Public/Granted day:2007-09-27
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