Invention Grant
- Patent Title: Method to align mask patterns
- Patent Title (中): 对齐掩模图案的方法
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Application No.: US10934317Application Date: 2004-09-02
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Publication No.: US07655387B2Publication Date: 2010-02-02
- Inventor: Gurtej S. Sandhu , Randal W. Chance , William T. Rericha
- Applicant: Gurtej S. Sandhu , Randal W. Chance , William T. Rericha
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Knobbe, Martens, Olson & Bear LLP
- Main IPC: G03F7/00
- IPC: G03F7/00

Abstract:
Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction. In the other direction, use of photolithography and a shadowing effect caused by the relative heights of the photoresist and the narrow mask lines causes the wider mask lines to be formed with a rounded corner, thus increasing alignment tolerances in that direction by increasing the distance to a neighboring narrow mask line.
Public/Granted literature
- US20060046201A1 Method to align mask patterns Public/Granted day:2006-03-02
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