Invention Grant
- Patent Title: Wafer level package with good CTE performance
- Patent Title (中): 晶圆级封装具有良好的CTE性能
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Application No.: US12141138Application Date: 2008-06-18
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Publication No.: US07655501B2Publication Date: 2010-02-02
- Inventor: Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
- Applicant: Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
- Applicant Address: TW Hsinchu County
- Assignee: Advanced Chip Engineering Technology Inc.
- Current Assignee: Advanced Chip Engineering Technology Inc.
- Current Assignee Address: TW Hsinchu County
- Agency: Kusner & Jaffe
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.
Public/Granted literature
- US20080248614A1 WAFER LEVEL PACKAGE WITH GOOD CTE PERFORMANCE Public/Granted day:2008-10-09
Information query
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