Invention Grant
- Patent Title: Method for fabricating semiconductor package with stacked chips
- Patent Title (中): 制造具有堆叠芯片的半导体封装的方法
-
Application No.: US11649144Application Date: 2007-01-02
-
Publication No.: US07655503B2Publication Date: 2010-02-02
- Inventor: Jung-Pin Huang , Chin-Huang Chang , Chung-Lun Liu
- Applicant: Jung-Pin Huang , Chin-Huang Chang , Chung-Lun Liu
- Applicant Address: TW
- Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee Address: TW
- Agency: Edwards Angell Palmer & Dodge LLP
- Agent Peter F. Corless; Steven M. Jensen
- Priority: TW93123055A 20040802
- Main IPC: H01L21/50
- IPC: H01L21/50

Abstract:
A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.
Public/Granted literature
- US20070108571A1 Method for fabricating semiconductor package with stacked chips Public/Granted day:2007-05-17
Information query
IPC分类: