Invention Grant
- Patent Title: Semiconductor device free of gate spacer stress and method of manufacturing the same
- Patent Title (中): 没有栅间隔应力的半导体器件及其制造方法
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Application No.: US11848991Application Date: 2007-08-31
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Publication No.: US07655525B2Publication Date: 2010-02-02
- Inventor: Sun-jung Lee , Hong-jae Shin , Bong-seok Suh
- Applicant: Sun-jung Lee , Hong-jae Shin , Bong-seok Suh
- Applicant Address: KR Suwon-Si, Gyeonggi-Do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-Si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2006-0084852 20060904
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/8238 ; H01L21/4763

Abstract:
A semiconductor device that prevents gate spacer stress and physical and chemical damages on a silicide region, and a method of manufacturing the same, according to an exemplary embodiment of the present invention, includes a substrate, isolation regions formed in the substrate, a gate pattern formed between the isolation regions on the substrate, an L-type spacer adjacent to the sidewall of the gate pattern and extended to the surface of the substrate, source/drain silicide regions formed on the substrate between the end of the L-type spacer extended to the surface of the substrate and the isolation regions, via plugs electrically connected with the source/drain silicide regions, an interlayer dielectric layer which is adjacent to the L-type spacer and which fills the space between the via plugs layer formed on the gate pattern and the substrate, and a signal-transfer line formed on the interlayer dielectric layer.
Public/Granted literature
- US20080079089A1 Semiconductor Device Free of Gate Spacer Stress and Method of Manufacturing the Same Public/Granted day:2008-04-03
Information query
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