Invention Grant
US07655962B2 Enhancement mode insulated gate heterostructure field-effect transistor with electrically isolated RF-enhanced source contact
有权
增强型绝缘栅极异质结构场效应晶体管,具有电隔离RF增强型源极接触
- Patent Title: Enhancement mode insulated gate heterostructure field-effect transistor with electrically isolated RF-enhanced source contact
- Patent Title (中): 增强型绝缘栅极异质结构场效应晶体管,具有电隔离RF增强型源极接触
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Application No.: US11781338Application Date: 2007-07-23
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Publication No.: US07655962B2Publication Date: 2010-02-02
- Inventor: Grigory Simin , Michael Shur , Remigijus Gaska
- Applicant: Grigory Simin , Michael Shur , Remigijus Gaska
- Applicant Address: US SC Columbia
- Assignee: Sensor Electronic Technology, Inc.
- Current Assignee: Sensor Electronic Technology, Inc.
- Current Assignee Address: US SC Columbia
- Agency: Hoffman Warnick LLC
- Agent John W. LaBatt
- Main IPC: H01L29/778
- IPC: H01L29/778

Abstract:
Aspects of the present invention provide an enhancement mode (E-mode) insulated gate (IG) double heterostructure field-effect transistor (DHFET) having low power consumption at zero gate bias, low gate currents, and/or high reliability. An E-mode HFET in accordance with an embodiment of the invention includes: top and bottom barrier layers; and a channel layer sandwiched between the bottom and the top barrier layers, wherein the bottom and top barrier layers have a larger bandgap than the channel layer, and wherein polarization charges of the bottom barrier layer deplete the channel layer and polarization charges of the top barrier layer induce carriers in the channel layer; and wherein a total polarization charge in the bottom barrier layer is larger than a total polarization charge in the top barrier layer such that the channel layer is substantially depleted at zero gate bias.
Public/Granted literature
- US20080203430A1 ENHANCEMENT MODE INSULATED GATE HETEROSTRUCTURE FIELD-EFFECT TRANSISTOR Public/Granted day:2008-08-28
Information query
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