Invention Grant
US07655972B2 Structure and method for MOSFET with reduced extension resistance
有权
具有降低延伸电阻的MOSFET的结构和方法
- Patent Title: Structure and method for MOSFET with reduced extension resistance
- Patent Title (中): 具有降低延伸电阻的MOSFET的结构和方法
-
Application No.: US11164378Application Date: 2005-11-21
-
Publication No.: US07655972B2Publication Date: 2010-02-02
- Inventor: Dureseti Chidambarrao , Carl Radens
- Applicant: Dureseti Chidambarrao , Carl Radens
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Joseph P. Abate, Esq.
- Main IPC: H01L29/94
- IPC: H01L29/94
Abstract:
The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.
Public/Granted literature
- US20070114611A1 STRUCTURE AND METHOD FOR MOSFET WITH REDUCED EXTENSION RESISTANCE Public/Granted day:2007-05-24
Information query
IPC分类:
