Invention Grant
- Patent Title: Method for manufacturing semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路器件的制造方法
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Application No.: US11738741Application Date: 2007-04-23
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Publication No.: US07655993B2Publication Date: 2010-02-02
- Inventor: Ryoichi Furukawa , Satoshi Sakai , Satoshi Yamamoto
- Applicant: Ryoichi Furukawa , Satoshi Sakai , Satoshi Yamamoto
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corporation
- Current Assignee: Renesas Technology Corporation
- Current Assignee Address: JP Tokyo
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP2001-350636 20011115
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
Public/Granted literature
- US20070187764A1 METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2007-08-16
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