Invention Grant
- Patent Title: Multilayer wiring substrate, method of manufacturing the same, and semiconductor device
- Patent Title (中): 多层布线基板及其制造方法以及半导体装置
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Application No.: US12205057Application Date: 2008-09-05
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Publication No.: US07656013B2Publication Date: 2010-02-02
- Inventor: Michio Horiuchi , Fumimasa Katagiri , Shigeaki Suganuma , Yasue Tokutake , Jun Yoshiike
- Applicant: Michio Horiuchi , Fumimasa Katagiri , Shigeaki Suganuma , Yasue Tokutake , Jun Yoshiike
- Applicant Address: JP Nagano
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano
- Agency: Drinker Biddle & Reath LLP
- Priority: JP2007-231692 20070906
- Main IPC: H01L23/495
- IPC: H01L23/495

Abstract:
There is provided a multilayer wiring substrate on which at least one semiconductor element is mounted. The multilayer wiring substrate includes: a baseboard; a first wiring layer formed on the baseboard and having a plurality of first wiring portions; an insulating layer formed on the baseboard; a second wiring layer formed on the insulating layer and having a plurality of second wiring portions, the second wiring portions being electrically connected to each other via a conductor wire, the conductor wire being arranged within the insulating layer three-dimensionally in a curved manner; and conductor portions configured to pass through the insulating layer and connecting the first wiring portions and the second wiring portions.
Public/Granted literature
- US20090072370A1 MULTILAYER WIRING SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE Public/Granted day:2009-03-19
Information query
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