Invention Grant
- Patent Title: C4 joint reliability
- Patent Title (中): C4联合可靠性
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Application No.: US12351689Application Date: 2009-01-09
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Publication No.: US07656035B2Publication Date: 2010-02-02
- Inventor: Sairam Agraharam , Carlton Hanna , Dongming He , Vasudeva Atluri , Debendra Mallik , Matthew Escobido , Sujit Sharan
- Applicant: Sairam Agraharam , Carlton Hanna , Dongming He , Vasudeva Atluri , Debendra Mallik , Matthew Escobido , Sujit Sharan
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L23/485
- IPC: H01L23/485

Abstract:
In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.
Public/Granted literature
- US20090115057A1 C4 JOINT RELIABILITY Public/Granted day:2009-05-07
Information query
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