Invention Grant
- Patent Title: CMOS device with asymmetric gate strain
- Patent Title (中): 具有不对称栅极应变的CMOS器件
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Application No.: US11315031Application Date: 2005-12-22
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Publication No.: US07656049B2Publication Date: 2010-02-02
- Inventor: Gurtej S. Sandhu , Kunal R. Parekh
- Applicant: Gurtej S. Sandhu , Kunal R. Parekh
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: H01L27/088
- IPC: H01L27/088

Abstract:
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain is obtained through non symmetric placement of stress inducing structures as part of the gate electrode. Silicon nitride layers may be placed on one side of the gate electrode in a compressive mode, or on the other side of the gate electrode in a tensile mode to obtain similar results.
Public/Granted literature
- US20070145430A1 CMOS device with asymmetric gate strain Public/Granted day:2007-06-28
Information query
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