Invention Grant
- Patent Title: Multilayer wiring board and method for testing the same
- Patent Title (中): 多层接线板及其测试方法
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Application No.: US12072703Application Date: 2008-02-27
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Publication No.: US07656166B2Publication Date: 2010-02-02
- Inventor: Yoshiyuki Fukami
- Applicant: Yoshiyuki Fukami
- Applicant Address: JP Musashino-shi, Tokyo
- Assignee: Micronics Japan Co., Ltd.
- Current Assignee: Micronics Japan Co., Ltd.
- Current Assignee Address: JP Musashino-shi, Tokyo
- Agency: Frishauf, Holtz, Goodman & Chick, P.C.
- Priority: JP2007-049193 20070228
- Main IPC: G01R31/02
- IPC: G01R31/02 ; G01R27/26

Abstract:
A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. The ceramic substrate has an internal conductor layer, which is connected to a test pad. The first conductor layer is formed, and then an electric capacitance is measured between the test pad and a wiring pattern of the first conductor layer. On the other hand, an electrical capacitance is calculated under the normal wiring pattern condition. The measured value is compared to the calculated value to determine whether the wiring pattern is good or bad. Similar measurements and comparisons are carried out for each of the second through fifth conductor layers to determine whether a three-dimensional wiring path is good or bad. As the ceramic substrate has an internal conductor layer, the electric capacitance of the wiring can be measured without an overall grounded layer in the multilayer wiring section, which is a characteristic part different from others among a variety of the multilayer wiring boards.
Public/Granted literature
- US20080204037A1 Multilayer wiring board and method for testing the same Public/Granted day:2008-08-28
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