A test apparatus capable of detecting input/output (I/O) circuit characteristics of a semiconductor device by analyzing an eye mask generated in the test apparatus and the waveform of a test signal output from the I/O circuit of the semiconductor device. The test apparatus includes an eye mask generator that generates an eye mask in synchronization with one or more clock signals of opposite phase to each other, an error detector that receives the eye mask from the eye mask generator and compares the test signal with the eye mask to determine whether an error occurs in the semiconductor device, and an error signal output unit that receives an error detection signal from the error detector and generates an error signal in response to the error detection signal. In particular, the eye mask generator includes a sine wave generator that generates one or more sine waves of opposite phase to each other in synchronization with one or more clock signals, and a limiter circuit that receives the sine waves and generates the eye mask by adjusting the amplitudes of the sine waves.