Invention Grant
- Patent Title: Three dimensional integrated circuits
- Patent Title (中): 三维集成电路
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Application No.: US12254629Application Date: 2008-10-20
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Publication No.: US07656192B2Publication Date: 2010-02-02
- Inventor: Raminda Udaya Madurawe
- Applicant: Raminda Udaya Madurawe
- Applicant Address: US CA Santa Clara
- Assignee: Tier Logic, Inc
- Current Assignee: Tier Logic, Inc
- Current Assignee Address: US CA Santa Clara
- Agency: Tran & Associates
- Main IPC: G06F7/38
- IPC: G06F7/38 ; H03K19/177

Abstract:
A programmable integrated circuit (IC), comprising: a programmable logic circuit configured by a first control signal coupled to a gate electrode of a transistor in the logic circuit; and a first plurality of read only memory (ROM) elements capable of coupling to the first control signal, wherein a said first ROM elements is selected to couple by one or more decode signals, and wherein the first ROM elements store a plurality of user specifications.
Public/Granted literature
- US20090039918A1 THREE DIMENSIONAL INTEGRATED CIRCUITS Public/Granted day:2009-02-12
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