Invention Grant
- Patent Title: Output buffer circuit
- Patent Title (中): 输出缓冲电路
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Application No.: US11516594Application Date: 2006-09-07
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Publication No.: US07656201B2Publication Date: 2010-02-02
- Inventor: Teruaki Kanzaki
- Applicant: Teruaki Kanzaki
- Applicant Address: JP Chiyoda-Ku, Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Chiyoda-Ku, Tokyo
- Agency: Buchanan Ingersoll & Rooney PC
- Priority: JP2005-267936 20050915
- Main IPC: H03K3/00
- IPC: H03K3/00

Abstract:
When a first signal is switched from an L level to an H level and a second signal is switched from an H level to an L level, and a first constant current source cannot follow the switching immediately thereafter and has not yet been switched, a first node remains at an H level, so an output node remains at an L level. In such state, a second node having been connected to a third node of an H level before the switching becomes connected to the first node of an H level by the switching. At the same time, the output part of an inverter is switched from an H level to an L level, causing the second node to be switched from an H level to an L level as well via a capacitor. At this time, the potential of the first node is reduced to become equal to the second node, to make a transition to an L level.
Public/Granted literature
- US20070057705A1 Output buffer circuit Public/Granted day:2007-03-15
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