A receiving circuit is provided for receiving a data signal and a clock signal, which are RSDS signals, and outputting an output data signal to a data driver. The receiving circuit includes a data comparator, a data intermediate circuit, a clock comparator, a clock intermediate, and a flip-flop. The data comparator, driven with a data bias current, receives the data signal, and outputs a compared data signal. The clock comparator, driven with a clock bias current, receives the clock signal, and outputs a compared clock signal. The flip-flop receives the compared data signal via the data intermediate circuit and the compared clock signal via the clock intermediate circuit. The phase difference between the compared data signal and the compared clock signal is improved by adjusting the data and the clock bias currents.