Invention Grant
- Patent Title: Voltage generation circuit and semiconductor memory device including the same
- Patent Title (中): 电压产生电路和包括其的半导体存储器件
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Application No.: US11739397Application Date: 2007-04-24
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Publication No.: US07656225B2Publication Date: 2010-02-02
- Inventor: Katsuaki Isobe , Noboru Shibata
- Applicant: Katsuaki Isobe , Noboru Shibata
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2006-119772 20060424
- Main IPC: G05F1/10
- IPC: G05F1/10 ; G05F3/02
Abstract:
A voltage generation circuit comprises a reference voltage generation circuit; a differential amplifier; an output node; a P-channel MOS transistor; a first resistor series; a second resistor series; a third resistor series; and a selection control circuit. A reference voltage generated by the reference voltage generation circuit is input to a first input terminal of the differential amplifier. The first resistor series is connected between a drain of the P-channel MOS transistor and the output node. The second resistor series is connected between the output node and a second input terminal of the differential amplifier. The third resistor array is connected between the second input terminal of the differential amplifier and a ground. The selection control circuit controls such that a sum of the resistances of the first resistor series and the second resistor series is constant.
Public/Granted literature
- US20070247133A1 VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME Public/Granted day:2007-10-25
Information query
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