In a signal processing arrangement, a digital-to-analog converter (DAC1) of the finite impulse response type converts a serial bitstream (BSL) into an analog output signal (AL). The digital-to-analog converter (DAC1) comprises at least two current source arrays (CCA1, CC A2). In a first current source array (CCA1), a current definition cell (CD1) generates a first basic current, and a plurality of first current copy cells ( . . . , CC40, CC41, . . . ) provide respective scaled copies of the first basic current to constitute first filter coefficient currents ( . . . , IP40, IP41, . . . ). In a further current source array (CCA2), a further current definition cell (CD2) generates a further basic current, and a plurality of current further copy cells (CC1, CC2, . . . , CC80) provide respective scaled copies of the further basic current to constitute further filter coefficient currents (IP1, IP2, . . . , IP80). A switch-and-shift array (XSA) individually passes the respective filter coefficient currents (IP1, IP2, . . . , IP40, IP41, . . . , IP80) to a signal output (CVC), or to another point (DLD), depending on respective successive bit values in the serial bitstream (BSL).