Invention Grant
- Patent Title: Solid-state imaging apparatus having gate potential that is negtive with respect to a well region
- Patent Title (中): 具有相对于阱区域为负的栅极电位的固态成像装置
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Application No.: US11728140Application Date: 2007-03-23
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Publication No.: US07656449B2Publication Date: 2010-02-02
- Inventor: Ryoji Suzuki , Takahisa Ueno , Keiji Mabuchi
- Applicant: Ryoji Suzuki , Takahisa Ueno , Keiji Mabuchi
- Applicant Address: JP Tokyo
- Assignee: Sony Corporation
- Current Assignee: Sony Corporation
- Current Assignee Address: JP Tokyo
- Agency: Rockey, Depke & Lyons, LLC
- Agent Robert J. Depke
- Priority: JP2001-340440 20011106
- Main IPC: H04N3/14
- IPC: H04N3/14 ; H04N9/64 ; H01L27/148 ; H01L31/062

Abstract:
Each unit pixel includes a photodiode, a reading selection transistor, a reading transistor, an amplifying transistor, a reset transistor, and a horizontal selection transistor, and thus a MOS image sensor of a dot-sequential reading 5-Tr type is formed. The reading selection transistor and the reading transistor are formed with a two-layer gate structure, and gate potential of the reading selection transistor and the reading transistor is set to a negative potential. Thereby, a lower layer of a gate region of the reading transistor and the reading selection transistor is controlled to a negative potential. Thus, depletion in the lower layer region is suppressed to reduce leakage current.
Public/Granted literature
- US20070177041A1 Solid-state imaging apparatus and driving method thereof Public/Granted day:2007-08-02
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