Invention Grant
US07656702B2 Ultra low voltage, low leakage, high density, variation tolerant memory bit cells
有权
超低电压，低泄漏，高密度，耐变容容量的存储单元
- Patent Title: Ultra low voltage, low leakage, high density, variation tolerant memory bit cells
- Patent Title (中): 超低电压，低泄漏，高密度，耐变容容量的存储单元
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Application No.: US12006288Application Date: 2007-12-31
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Publication No.: US07656702B2Publication Date: 2010-02-02
- Inventor: Sapumal Wijeratne , Matthew W. Ernest , Brian A. Kuns
- Applicant: Sapumal Wijeratne , Matthew W. Ernest , Brian A. Kuns
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Caven & Aghevli LLC
- Main IPC: G11C11/40
- IPC: G11C11/40
Abstract:
Methods and apparatus to provide ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells are described. In one embodiment, each of the cross-coupled invertors of a memory cell may include a plurality of p-channel transistors. Other embodiments are also described.
Public/Granted literature
- US20090168509A1 Ultra low voltage, low leakage, high density, variation tolerant memory bit cells Public/Granted day:2009-07-02
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