Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.