Invention Grant
US07656907B2 Method and apparatus for reducing clock speed and power consumption 有权
降低时钟速度和功耗的方法和设备

Method and apparatus for reducing clock speed and power consumption
Abstract:
A system for reducing clock speed and power consumption in a network chip is provided. The system can have a core that transmits and receives signals at a first clock speed. A receive buffer can be in communication with the core and be configured to transmit the signals to the core at the first clock speed. A transmit buffer can be in communication with the core and configured to receive signals from the core at the first clock speed. A sync can be configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync can be in communication with the transmit buffer and the receive buffer.
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