Invention Grant
US07656945B1 Stabilized digital timing recovery using low-complexity equalizer
有权
使用低复杂度均衡器稳定的数字定时恢复
- Patent Title: Stabilized digital timing recovery using low-complexity equalizer
- Patent Title (中): 使用低复杂度均衡器稳定的数字定时恢复
-
Application No.: US11538346Application Date: 2006-10-03
-
Publication No.: US07656945B1Publication Date: 2010-02-02
- Inventor: William D. Warner , Paul V. Yee
- Applicant: William D. Warner , Paul V. Yee
- Applicant Address: US CA Santa Clara
- Assignee: PMC-Sierra, Inc.
- Current Assignee: PMC-Sierra, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Knobbe Martens Olson & Bear LLP
- Main IPC: H03H7/40
- IPC: H03H7/40

Abstract:
A low-complexity digital linear equalizer whose operation and adaptation makes stabilized digital timing recovery practical. The technique is fundamental for the operation of communications receivers employing digital timing recovery, e.g., in a modem. A technique for automatically adjusting the parameters of a digital linear equalizer to compensate for low-pass impairments while maintaining a relatively constant timing characteristic is described.
Information query