Invention Grant
- Patent Title: Dual clock domain deskew circuit
- Patent Title (中): 双时钟域偏移电路
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Application No.: US11541427Application Date: 2006-09-29
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Publication No.: US07656983B2Publication Date: 2010-02-02
- Inventor: Daniel S. Klowden , S. Reji Kumar , Adarsh Panikkar , Kersi H. Vakil , Abhimanyu Kolla
- Applicant: Daniel S. Klowden , S. Reji Kumar , Adarsh Panikkar , Kersi H. Vakil , Abhimanyu Kolla
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Ryder, Lu, Mazzeo and Konieczny, LLC
- Agent Douglas J. Ryder
- Main IPC: H04L7/00
- IPC: H04L7/00 ; H04L25/00 ; H04L25/40

Abstract:
In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.
Public/Granted literature
- US20080080654A1 Dual clock domain deskew circuit Public/Granted day:2008-04-03
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