A memory that includes a plurality of packet pins, a synchronous memory, and a packet controller. The synchronous memory receives address and control signals in synchronization with a clock signal. The packet controller sequentially receives packet data bits through the packet pins in synchronization with the clock signal when a packet enable signal is activated, and converts the inputted packet data into the address and control signals. Specifically, packet data bits that are first inputted through the packet pins represent an operation mode.