Invention Grant
- Patent Title: Semiconductor integrated circuit and the same checking method
- Patent Title (中): 半导体集成电路和相同的检查方法
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Application No.: US11645509Application Date: 2006-12-27
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Publication No.: US07657798B2Publication Date: 2010-02-02
- Inventor: Natsuki Kushiyama , Shigeaki Iwasa
- Applicant: Natsuki Kushiyama , Shigeaki Iwasa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2005-379456 20051228
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
A semiconductor integrated circuit has a cell array, a redundancy cell capable of replacing a defective cell, a redundancy control circuit, a plurality of first fuses, a plurality of second fuses, a plurality of third fuses, a first shift register configured to hold states of the plurality of first fuses, a second shift register configured to be connected in cascade to the first shift register and to hold states of the plurality of second fuses, a third shift register configured to be connected to the first and second shift registers in cascade and to hold states of the plurality of third fuses, a CRC remainder calculator configured to sequentially input information held by the first to third shift registers to a CRC generating equation to calculate a remainder obtained by division, and a CRC determination part that outputs information indicative of whether the first to third fuses are correctly programmed.
Public/Granted literature
- US20070226552A1 Semiconductor integrated circuit and the same checking method Public/Granted day:2007-09-27
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