Invention Grant
US07657805B2 Integrated circuit with blocking pin to coordinate entry into test mode
有权
具有阻塞引脚的集成电路,以协调进入测试模式
- Patent Title: Integrated circuit with blocking pin to coordinate entry into test mode
- Patent Title (中): 具有阻塞引脚的集成电路,以协调进入测试模式
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Application No.: US11772328Application Date: 2007-07-02
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Publication No.: US07657805B2Publication Date: 2010-02-02
- Inventor: Thomas Alan Ziaja , Kevin D. Woodling , Robert F. Molyneaux
- Applicant: Thomas Alan Ziaja , Kevin D. Woodling , Robert F. Molyneaux
- Applicant Address: US CA Santa Clara
- Assignee: Sun Microsystems, Inc.
- Current Assignee: Sun Microsystems, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Agent Robert C Kowert; Anthony M. Petro
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
An integrated circuit (IC) including a blocking pin. An IC may include state logic, a test control unit configured to coordinate access by external circuitry to operating state of the state logic during a test mode, and interface pins configured to couple the integrated circuit to the external circuitry. Shared interface pins may provide input signals to the test control unit during the test mode of operation and may perform distinct I/O functions during normal mode operation. A blocking interface pin, when asserted by external circuitry during normal mode operation, may force test signals derived from at least a portion of the shared interface pins by the test control unit into respective quiescent states, such that subsequent to assertion of the blocking pin, the integrated circuit is operable to enter the test mode of operation from the normal mode of operation without resetting operating state of the state logic.
Public/Granted literature
- US20090013224A1 INTEGRATED CIRCUIT WITH BLOCKING PIN TO COORDINATE ENTRY INTO TEST MODE Public/Granted day:2009-01-08
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