Invention Grant
- Patent Title: Dual scan chain design method and apparatus
- Patent Title (中): 双扫链设计方法及装置
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Application No.: US10718445Application Date: 2003-11-19
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Publication No.: US07657809B1Publication Date: 2010-02-02
- Inventor: Sandeep Bhatia
- Applicant: Sandeep Bhatia
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G01R31/28
- IPC: G01R31/28
Abstract:
A method for testing an integrated circuit includes scanning test data from an input and an output pin into a first scan chain during a first state of a clock cycle, and scanning test data from the same input and output pins into a second scan chain during a second state of the clock cycle.
Information query
