The programmable decoder, such as a Maximum Likelihood Sequence Estimation (MLSE) decoder (e.g. a Viterbi decoder) may include a programming input for a plurality of programmable trellis parameters, and a programmable device, such as an FPGA, connected to the programming input and implementing a trellis decoder including at least one trellis structure defined based upon the plurality of programmable trellis parameters. The plurality of programmable trellis parameters may include trellis connectivity information for trellis stages, active and inactive states for each trellis stage, a trellis branch transition data value and a metric index for trellis branch transition. Also, the trellis structure may include a reverse-state trellis structure. The programmable trellis decoder can decode convolutional codes, trellis coded modulation (TCM), ISI channels and CPM waveforms.